A semiconductor device including GaAs field effect transistors (FET's) used in a super high frequency band, for example, in a frequency band of from several gigahertz to tens of gigahertz, includes a number of unit FET's or groups of unit FET's which are connected in parallel on one single chip, in order to provide high output power.
FIG. 1 is a plan view of an example of a conventional semiconductor device including one group of unit transistors arranged on a chip. In FIG. 1, a plurality of unit FET's are disposed on a given active region formed on a substrate of, for example, GaAs, with drain electrodes 2 of the respective FET's being equally spaced to form a comb-like shape. Respective ends of the drain electrodes 2 are connected to a common drain electrode pad 3. Also, a plurality of source electrodes 4 are disposed in a comb-like form on the active region, with a predetermined spacing from adjacent drain electrodes 2. Respective ends of the source electrodes 4 are connected to a common source electrode pad 5. Gate electrodes 6 are disposed on the active region between adjacent drain and source electrodes. Respective ends of the gate electrodes 6 are connected to a common conductor 7 which, in turn, is connected to a gate electrode pad 8. At the intersections of the source electrodes 4 with the gate conductor 7, the source electrodes 4 pass over the conductor 7 with an insulating film and a gap interposed therebetween. Each gate electrode, associated source and drain electrode, and the associated active region in the substrate is referred to here as a unit transistor.
When the above-described semiconductor device is handling a signal of a frequency of from several gigahertz to tens of gigahertz the length Lg, along the channel direction, of the gate electrode 6 of each of the unit FET's is from about 0.4 .mu.m to about 0.7 .mu.m and the width Wg of each gate electrode 6 is 60-100 .mu.m so that parasitic components (e.g. gate resistance) which have significant effects on the characteristic of the device can be reduced and, therefore, reduction of the gain of the device can be prevented.
In order to obtain high output power from a conventional semiconductor device with the above-described structure, it is necessary to increase the total gate width by making the product of the width Wg of each gate electrode 6 and the number of gate electrodes large. However, in order to provide a larger total gate width with a small width of each gate electrode 6, the chip tends to be laterally elongated excessively. Accordingly, the width of each gate electrode should be limited. If a larger gate width Wg of each gate electrode is used, the signal phase at the terminating end of the gate electrode 6 deviates from the signal phase at the input end (i.e. that end which is connected to the gate conductor 7), so that the signal is distorted.
A structure of another conventional semiconductor device is shown in FIG. 2, which was proposed to eliminate the above-described disadvantages. In the structure illustrated in FIG. 2, the width Wg of the gate electrode of each unit FET is reduced to about one half, namely, from 30 .mu.m to 50 .mu.m, and the decrease in output power caused by the reduction of the width Wg of the gate electrodes is compensated for by increasing the number of groups of unit transistors used.
Referring to FIG. 2 and FIG. 3 which shows the cross-section along Y.sub.1 --Y.sub.1 in FIG. 2, a plurality of drain electrodes 21 of the unit FET's are disposed on a predetermined active region formed on a substrate of, for example, GaAs. The drain electrodes 21 are equally spaced from each other to form a comb-like shape. Respective ends of the drain electrodes 21 are connected to associated common drain electrode pads 31. Also a plurality of source electrodes 41 are formed on the active region with a given spacing disposed between adjacent drain electrodes 21. The source electrodes are disposed in a comb-like shape and have respective ends connected to a common source electrode pad 51. Gate electrodes 61 are disposed between adjacent drain and source electrodes 21 and 41. Respective ends of the gate electrodes 61 are connected to a common conductor 71 which, in turn, is connected to common gate electrode pads 81. As in the example shown in FIG. 1, in the case of FIG. 2, too, where the gate electrode conductor 71 intersects the source electrodes 41, the source electrodes 41 pass over the conductor 71 with an insulating film and a gap disposed therebetween.
The width Wg of each gate electrode of the semiconductor device of FIG. 2 is reduced to about one half the width in the device of FIG. 1, and, therefore, signal phase deviation between the input end of each gate electrode 61 (that end which is connected to the conductor 71) and the tip end is small. Thus, satisfactory characteristics are exhibited by the device even at a super high frequency of from several gigahertz to tens of gigahertz. Furthermore, since two groups 10 and 20 of unit transistors are provided, the reduction in output power which could caused by the reduction of the width Wg of the gate electrodes 61 can be compensated for, so that sufficiently high output can be obtained even at a super high frequency of from several gigahertz to tens of gigahertz.
The conventional semiconductor device shown in FIG. 2 has a structure in which the unit transistor groups 10 and 20 are arranged in a row. Accordingly, if a number of groups of unit transistors are arranged in a row in order to produce high output, the dimensional balance of the substrate chip would be lost and the substrate chip would become very long. If the chip becomes elongated, it tends to be easily broken during handling and also to warp. Furthermore, the number of bonding wires for applying an input signal increases, which introduces variations in length of the bonding wires, which, in turn, could cause input signal phase deviations. In addition, because the number of the gate electrode bonding pads 81 increases, fringing capacitance increases due to an increase in the number of the gate bonding pads 81 and wires connecting the respective gate electrodes to the gate bonding pads 81, so that high frequency characteristics are degraded.
A structure of a microwave high output transistor device with balanced dimensions of a substrate chip and with a number of FET's arranged on the chip to provide high output is shown, for example, in Japanese Published Patent Application No. SHO 60-37170. Its basic structure is shown in FIG. 4. Referring to FIG. 4, source electrodes 13A, 13B, 13C and 13D are disposed on a substantially square substrate 12. The source electrodes are disposed parallel to the sides of the square substrate 12. The source electrodes are connected to associated source electrode pads 14A, 14B, 14C and 14D. Drain electrodes 15A, 15B, 15C and 15D are connected to a common drain electrode pad 16 located in a central portion of the substrate 12. Gate electrodes 17A, 17B, 17C and 17D are located between source and drain electrodes that are adjacent to each other. The gate electrodes 17A and 17D are connected via associated gate connecting conductors 18A and 18B to a first gate electrode pad 19A, while the gate electrodes 17B and 17C are connected via associated gate connecting conductors 18B and 18C to a second gate electrode pad 19B.
The substrate chip of the semiconductor device disclosed in this Japanese Published Patent Application No. SHO 60-37170 which has the structure shown in FIG. 4 is square, and, accordingly, the tendency of the substrate to be broken or to warp is significantly reduced relative to the semiconductor device shown in FIG. 2. However, because some FET's (e.g. FET's of groups A and C) are orthogonal to the remaining FET's (e.g. FET's of groups B and D) on the substrate 12, FET's arranged in one direction and FET's arranged in the orthogonal direction are differently processed, e.g. etched, due to difference in crystal orientation. Furthermore, stresses applied by a surface protection film to FET's arranged in different directions are different. This causes the gate threshold voltage of the FET's of groups A and C to differ from that of the FET's of groups B and D. In addition, this structure requires that the drain electrode pad 16 be large, so that the substrate area must be large.
The object of the present invention is to eliminate all of the above-described problems, by providing a semiconductor device which includes a number of transistors, such as FET's, disposed on a chip having balanced longitudinal and lateral dimensions, with the numbers of bonding pads and bonding wires minimized so as to reduce the capacitances caused by bonding pads and wires. According to the present invention, the width Wg of the gate of a unit transistor is reduced so as to minimize input signal phase deviations and also gate resistance. Thus, the proposed semiconductor device can provide high output power at super high frequencies.